User Guide

The Validator Concept

The development of the Validator was motivated by a lack of existing tools for engineers and technicians to easily setup arbitrary stimulus and simple tests. To debug or validate or simply understand the performance of an IC, PCB, or bread- board, often requires a nontrivial investment in the stimulus setup, both in cost and time. The Validator delivers a simple straightforward method to allow the creation of any stimulus within Validator’s performance constraints. The key simplicity is in the method for inputting the pattern. Rather than create a unique interface, the ubiquitous spreadsheet was chosen as the vehicle for input. As with most engineering choices, there are trade-offs. The ease of creating a test file with a familiar software tool might be offset by discomfort with the visual presentation of the pattern or discomfort from a lack of experience at manipulating spreadsheets. While evaluating this trade-off, consider the following:

• Analog patterns are specified in volts at each time step. Type an amplitude number in the DAC column or type an equation as a function of the time column.
• The digital pattern can be 1 line or 4095 lines. Paste re- petitive stuff. Create often used routines like SPI codes in a template for simplified data entry.
• The CSV format (comma separated variables) is often avail- able from simulations or testers and could be pasted into the format.
• Share exact stimuli files in spreadsheet format by email. Download a shared file to the Validator immediately, without manipulations, to observe issues.
• The Validator was designed for creating parallel units of IO and DAC drive — in synchronization. Drive a system with two or more Validators in parallel without constraints.
• The Validator comes with standard waveform producing files that are easily customizable – or usable as is.

Another objective of the Validator was to provide the option to leave the computer at the desk. After downloads, a valid pattern is stored in nonvolatile memory. The Validator can be unplugged from the USB connection, transported to the lab, powered by any 5V supply, and with a push of the Load button, be ready to run the pattern standalone.

Test capability is included. DIO patterns change on the negative edge of the clock and are tested as inputs on the positive edge. Any channel can be tested for its logic state at any step by typing either TL or TH. Simple screening chores are possible.

The Validator offers program control possibilities. Stop on Fail, Pause, Jump, and Jump on Fail are tools to diagnose a response problem or to respond to input states with al- ternative patterns. For example, the ability to test any DIO channel at any step in the pattern and conditionally branch to a designated step, allows creative control setups. A number of DIO channels could be each tested for a parallel incoming code in an unconditional loop and when a match occurs, jump to a particular drive pattern or even another loop looking for another code.

Glossary

Pattern – Contents of a Comma Separated Variable (CSV) file in standard Validator 1 format. Includes Setup variables and contiguous Line data which together specify the Validator IO actions after the Run button is pressed.

Master Clock – The Master Clock source is chosen with the Setup variable “EXT CLK IN”. If Zero, the Master Clock is the internal 24Mhz oscillator. If One, the Master Clock comes from an external source whose frequency should be entered into the Setup spreadsheet cell H7.

Line Clock – Frequency is set by the Setup variable “Clock Divide” and is equal to the Master Clock divided by Clock Divide.

Line Period – Each Program Line has a “Number of Clocks” data entry. The Line Period is the Master Clock period times the “Number of Clocks”.

Control Panel – The software interface seen when the exe- cutable for the Windows host, Validator1_Host, is activated.

Breakout Board – Each Validator 1 comes with a PCB called the Breakout Board. It has connectors to attach the 16 DIO channels on two sides. On one side, the connectors only go to adjacent male header pins. A custom connector or socket could be attached and wired in the nearby uncommitted area. On the other side the DIO channels go to voltage translators. The 3.3V levels can be changed to any voltage from 1.6V to 5.5V.

Validator Features and Performance

• 16 Channels of independent arbitrary Digital Input Output (DIO) 3.3V
  • DC to 50 Mhz clocking patterns without commands
  • DC to 40 Mhz clocking with Jump, Jump Conditional, Number of Clocks Control, Stop on Fail, Pause, or Step.
• 5ns maximum skew between channels.
• Start pattern by Push Button or Host mouse click or with an edge selectable External Synch signal.
• Choose the Master Clock to be either the internal 24Mhz clock or an external clock.
• Choose a division of Master Clock from 1 to 1000 to create the Line Clock.
• Issue 1 to 1024 Line Clocks at each step of the pattern.
• Test any DIO channel at any step. Strobe is one half of a Line Clock from the end of the Line Period.
• Failed channels logged by host software and also indicated by a red Fail light.
• Two independent DAC channels, powered by an on-board +/- 15V switcher.
• DACs are DAC813 ICs configured for 10 bit resolution.
• DACs programmed in volts each line, from -10V to +10V, with 0.5% DC accuracy.
• Spreadsheet entry allows DAC voltages to be computed by formulas as a function of the elapsed time column.
• USB or standalone 5V powered. 250ma unloaded. If both the USB and 5V supply are connected, power is derived from the 5V supply.
• Nonvolatile memory records last valid program which can be reloaded with the Load button.
• Provisions to create multiple parallel Validators starting and running in synchronization.
• 4095 program steps maximum with up to 15 arbitrarily placed labels for Jump or Jump on Fail destinations.
• DIO Channels have weak pull downs (~38K) when config- ured as Open or Input and when the pattern is not running. Line by line configuration allows bus interfacing.
• The configured Line Clock can be output any DIO channel at any step by typing C at the step.

Validator Interface

Front Panel Connections

DACs

DAC1 and DAC2 outputs are located at the left two BNC connectors of the front panel.

DIO

DIO connections are made at two 8X2 Headers. Channels 15 through 8 are positioned on the top row of the left connector while Channels 7 through 0 are positioned on the top row of the right 8X2 connector. Bottom pins of both connectors are Ground.

ACC1 – TOP ROW

Pin 1 CLOCK OUT

Pin 1 is top right. In SETUP, this pin can be made active. It will output “The number of Line Clocks this Line” for every Line executed. Each Line Clock is equal to the Master Clock divided by the Setup Clock Divide.

Pin 3 FINISH

Goes Low at RUN and stays low until FINISH. FINISH is de ned as completion of the last Line of the submitted Pattern.

Pin 5 FAIL STROBE 8_15

Outputs a pulse at each Line’s Strobe if there is a Test Fail for Channels 8 to 15.

Pin 7 FAIL STROBE 0_7

Outputs a pulse at each Line’s Strobe if there is a Test Fail for Channels 0 to 7.

ACC1 – BOTTOM ROW

Pin 2  GROUND

Pin 4  Open

Pin 6  Open

Pin 8  3.3V

REAR PANEL CONNECTIONS

USB

In Figure 2, the USB connection is made at the far left with a type B connector.

Power

An alternative power source can be provided at the rear panel banana jacks. The left is GROUND and the right is 5V. Note if both the USB and 5V power are connected, the unit receives its power only from the banana connections.

External Trigger Input

Pattern Setup can choose an External Trigger to start the pattern. The left BNC as you view the Rear Panel receives the 3.3V signal edge. Note that Setup allows the choice of a positive edge or a negative edge.

External Clock Input

Setup allows a choice of the Master Clock source, Internal Clock or External Clock. The BNC to the right as you view the Rear Panel receives the 3.3V External Clock In signal. Note there is an option in Setup to make this BNC an output by selecting Master Clock Out (24 MHz). This is a convenient source of synchronized clocking of Validators wired in parallel. The “Slave” Validators would receive this Master Clock Out at their External Clock inputs. Thus all parallel units operate from the same clock.

ACC2 – TOP ROW

Pin 1  FACTORY TEST (Pin 1 is top right)

Pin 3  FACTORY TEST

Pin 5  TEST START OUT

This pin can drive TEST START IN (pin 7 below) for synchronous parallel Validator Units. For example if the application required 32 DIO and/or 4 DACs, a synchronous start can be achieved using TEST START OUT connected to the Slave unit TEST START IN. An additional requirement is for each unit to receive the same External Clock input. The Master unit which outputs TEST START OUT will control both units, either by pushbutton or a Control Panel click.

Pin 7  TEST START IN

Any number of “slave” units can be wired from the Master unit’s TEST START OUT to each of the Slave TEST START IN pins.

ACC2 – BOTTOM ROW

Pin 2  GROUND

Pin 4  GROUND

Pin 6  GROUND

Pin 8  GROUND

Quick Start – View a Sample Program

Spreadsheet Pattern Preparation

Any of the supplied demonstration patterns could be used as a template to modify and “save as” to create a new program. To make a new program for Download rst “save as” a worksheet with a new name. After modifying, then “save as” a CSV (comma delimited) file for the format needed to download to Validator.

Below is the file “DATA ENTRY BLANKSHEET” which could be used repeatedly for this purpose. To change the number of lines, delete or paste whole rows. A paste should be from a copy of an existing line to allow auto-indexing formulas.

The CSV format is xed and cannot be changed regarding the positions of SETUP DATA, row 7, and LINE DATA, starting at row 19. To avoid nonsensical operation, programs are error checked before download. If errors are found, the Line number refer- enced is not the Spreadsheet line but rather the Line number found in Column A.

Hardware and Software Controls and Displays

Buttons

Hardware has 4 buttons which perform the same tasks as the software Control Panel buttons. The only difference is that the LOAD button on the hardware will cause the last valid pattern, which is automatically stored in Nonvolatile Memory, to be loaded. You might verify this feature by unplugging the USB cable and after a few seconds power the board at the banana jacks with a 5V supply (or even with the USB again). Once powered again, the READY light will turn “On” after you press the hardware LOAD button and the last program downloaded to the hardware will be ready to run. You can program the Validator at your desk top and then un-tether from the computer and load/execute the program on the bench.

When USB is connected, either type of button can be used to operate the Validator for the other 3 control buttons, Run, Step, and Reset.

Displays

The software Control Panel provides information about the Validator state.

Status

Possible status indications are LOAD, READY, RUN, PAUSE, JUMP, SOF and FINISH. JUMP only applies if viewing after a Pause Command and stepping encounters a Jump.

Line Number

The Line Number is useful when using Stop on Fail mode. The Line Number can also be useful after a Pause.

Fail Channels

If the result of a TH or TL is a Fail, then the host program appends the failed channel(s) to this display. After the program Finishes or Pauses, this display will show all fails encountered while executing each Line.

NOTE: USB communication of the Status, Line Number, and Fail Channels can be lost due to sequencing on some models of Windows computers. It is always recovered by unplugging the USB connection and then plugging it in again and reconnecting.

Commands Example

The pattern “Decaying Sine and Triangle” has no commands. To illustrate the use of commands, download the pattern “Commands Demo” to the Validator:

Press Run and observe that the Control Panel shows Pause at Line 4 and the Pause light is On. The scope trace below shows the execution of the pattern from start until halted at Line 4.

Next you have the choice to press Run again or press Step:

Step action – the Control Panel will show that at the next line the STATUS = JUMP and the program execution is halted again at Line 5.

Run action – if instead Run was pressed, STATUS = PAUSE and the program execution proceeded past the Jump to the next Pause at Line 8.

Jump if Fail

At Line 7, there is a JF command. Because DIO_7 is oating and there is a pulldown at every DIO channel, the TL entry, Test to be Low, will not fail. Since it did not fail, the program did not jump and hence the Pause at Line 8.

Change the TL command to TH, save as a CSV file, and download again. Now there will be a fail at Line 7. Run the pattern with the change and observe that the execution of the program will Jump to the FINISH if Run is pressed or Step to Line 10 if Step is pressed. Note that in this case, the Control Panel window “Fail Channels”, will continuously show D7 after Line 7 is executed. All fails are latched and the Fail Channels window will add any additional fail tests to the list as the program continues executing.

SOF

In Setup, there is an option to set the Stop on Fail control to a One. If that option is chosen, execution of th program is stopped at the first FAIL and cannot be continued after that. This option is intended to allow discovery of the first failure in a long pattern without resorting to tedious scope work looking for the first Fail Strobe and determining where it is exactly in the pattern.

LOOPING

With the Jump and Jump if Fail commands, it is possible to set up continuous or conditional looping. An example of continuous looping is available in the pattern “Sine and Cosine Loop”.

To stop the loop, press Reset or Download.

DIO Timing

At high speed, the delays between the clocks and DIO channels become a significant portion of the Line execution. The spread-sheet “Show Timing” can be used to illustrate the relationships and quantify the delays.

First observe the results below when the Clock Divide set-up, Cell B7, is changed from 1 above to 24. The Line Clock frequency becomes 1 Mhz (24Mhz/24 = 1 Mhz).

In the traces above, FINISH and CLK are output from the ACC1 header, pins 3 and 1 respectively. FAIL_0_7 and FAIL_8_15 are output from ACC1 at pins 7 and 5 respectively.

After the RUN button was depressed:

1. FINISH goes Low and the DIO channels achieve their initial state specified in Line 1.
2. DIO_8 outputs the same signal as CLK because it is programmed C.
3. DIO channels change state on the falling edge of the last Line Clock.
4. The pattern specified in column C supplies 1 Line Clock for the first line, 2 Line Clocks for the second line, and 3 Line Clocks for the third line.
5. At Line 2, DIO_7 was tested to be High. The pin was left open and failed because of the pull-down. The strobe occurred at the last Line Clock of Line 2.
6. When the last Line Clock goes low, FINISH goes High. The DIO channels are floating with a weak pull-down after Finish goes High. The transition to Low will be delayed by loading.

Below is the same scope setup with the Clock Divide set to 1 (24Mhz).

Delays are now evident. Relative to the CLK trace, DIO channels take about 10ns before they change state after the CLK went Low. Feeding the Master Clock into DIO_8 shows it is also delayed about 8ns using the CLK trace as a reference. Again with the CLK trace as reference, the FAIL0_7 positive edge is about 14ns behind the CLK positive edge.

50 Mhz

At 50 Mhz, the delay relationships are again magni ed. Below the same program was changed to run with an External Clock. (Note: Correct operation with Number of Clocks per step varying is only guaranteed to 40Mhz. The actual maximum will vary.)

DACs

Specifications for the DACs performance can be found in the datasheet of the DAC813 integrated circuit. Only the top 10 bits are used while the lower 2 bits are connected to Ground. Supplies are +/- 15V and the output range is set at +10V to -10V. When FINISH is high, that is, no pattern is running, the DAC outputs are driven to 0V.

Key specifications:

DC accuracy  – 0.5%

Slew Rate – 10 volts per usec

Settling Time – typical 4.5 usec

Output Current – 5 ma minimum

Below is a scope trace for the program “Sine and Cosine Loop Hi Speed”. DAC1 is set at a peak amplitude of 1V with a frequency of 1 Mhz while DAC2 peak is 5V at a frequency of 500 Khz.

At 1Mhz, the waveforms show the limitations of the DAC’s performance, particularly with offset and reduced peak voltages.

Parallel Units

Below is an example of a parallel setup yielding 4 DACs and 32 DIO channels operating in synchronization.The unit on the left feeds its internal clock to the unit on the right. In SETUP for the left unit, enter a One in cell G7, the Master CLK OUT selection. Both units have EXT CLK IN, Cell A7, set to a One. The jumper wire is connecting the left unit ACC2, pin 5, to the right unit ACC2, pin 7. This connection allows both units to start with one button push at the left unit.

MASTER / SLAVE CONNECTIONS

To achieve a synchronous start of all units together, one unit is designated the Master Unit and the other(s) are the Slave Units. At the rear ACC2 header connection of the Master unit connect Pin 5, Test Start Out, to all Slave Units Pin 7, Test Start In.

There are two options for creating a synchronous Master Clock. One is to simply wire an external source to all EXT CLK pins and, in the Setup selections, set cell A7, EXT CLK IN, to a One for all units.

Another option is to use the internal oscillator of the Master Unit. In Setup, Master Clock Out, cell G7, is set to a One, only for the Master Unit. This will cause the EXT CLK IN input to change to an output. The signal output is the 24 Mhz oscillator. The Setup of the Master and Slave Units need EXT CLK IN, cell A7, set to a 1. Wire all Slave EXT CLK IN BNCs to the Master EXT CLK IN BNC. Each Validator is loaded with its own program.

Key to synchronous parallel operation is integrity of the clock source. If the objective is to run several parallel units near the maximum Master Clock frequency, the driving source and connections to create the External Clock inputs must adequately drive each EXT CLK IN.

Channel to channel skew is affected by the clock source. It the Master is the clock source, expect up to 10 nsec of skew from Master channels to Slave channels. If the clock source is external, skew is tighter – typically within 3 nsec.

Breakout Board

Each Validator is shipped with a Breakout Board. The Breakout Board has two alternative purposes:

1. To facilitate wiring the DIO channels to a connector or socket. Place a connection device in the breakout area and wire to the headers on the right above
2. To translate DIO High Levels to another voltage anywhere between 1.6V and 5.5V.

TRANSLATING DIO CHANNEL HIGH LEVELS UP OR DOWN

Voltage translation of the DIO High Levels is available by connecting the DIO channels to the headers on the left above. To preserve the choice of making each channel independently an Input or Output, half of the 16 DIO channels must be dedicated to controlling the direction choice. The header at bottom above offers the resulting 8 translated IO channels.

The sample pattern “BREAKOUT VOLTAGE TRANSLATE” provides a convenient format to create translated IO. Refer to the “Guide to Using Sample Patterns” for more information about using this sample pattern.

To use the translator, a 5V supply must be connected to the red and black terminals above. If the objective is to translate to
5V, then a jumper connected to the left option will route the same 5V to the translators and it will be unnecessary to connect a translation supply to the yellow terminal. Otherwise the jumper should be connected to the right option and the desired translation level supply connected to the yellow terminal.

Below is a schematic of the Breakout Board translators.

Breakout Board – Schematic of DIO Channels Voltage Translator

VALIDATOR 1

Conditions: VEXT = 5.0V, temperature ambient = 25C, Master Clock is the Internal 24Mhz